1usmus - SQ AGENT: how one core can hold boost back

Meet SQ AGENT 1.3 and explore core #15 on a Ryzen 9 9950X3D

SQ AGENT in HYDRA helps assess the quality of your particular silicon through its behavior in a real PC. It shows how the processor performs with your cooling and settings: how much voltage each core requests, how hot it runs, and what effective clock it delivers.

Strong, sustained boost benefits from cores converging within a CCD: in voltage, temperature, and power demand.

Why SQ AGENT exists

A conventional benchmark gives you a final score. SQ AGENT reveals what individual cores are doing: their voltage requests, effective clocks, temperatures, and power. This helps explain a disappointing tuning result even when a test finishes without errors.

Silicon quality shows up in how cores turn voltage requests and power demand into effective clock speed. SQ combines these indicators with thermal behavior. You get a practical assessment of your particular processor in your system, alongside its factory core ranking.

A CCD is a chiplet containing a group of CPU cores. In this example, CCD#0 contains C0–C7 and CCD#1 contains C8–C15. We compare cores with their neighbors inside the same CCD, since separate chiplets can behave differently, especially on X3D processors.

The tuning idea is simple: bring the curves of cores within one CCD closer together across the operating range. A core that requests more voltage or runs hotter at the same speed may use headroom that boost needs. That makes temperature convergence as relevant as VID convergence.

Precision Boost raises clocks while temperature, power, current, and frequency limits allow it. Core convergence helps identify unnecessary demands on that headroom. It is a practical tuning goal. A repeat test in your workload determines the actual benefit.

Cooling has a major influence. Cooler contact, heat removal, and ambient temperature affect operating temperatures and available boost headroom. The same CPU can behave differently and receive a different SQ score after a cooling change. The result therefore reflects silicon, settings, and your cooling system working together.

The goal is to reduce meaningful outliers while maintaining stability. Identical CO values across all cores do not produce identical behavior.

What SQ AGENT tests and where its changes go

SQ AGENT tests your current profile from the AMD PBO2 tab. Its per-core CO values, power and current limits, temperature limit, and boost settings define the measurement conditions. Check that profile before starting.

Every CO adjustment you accept through SQ AGENT goes to the core settings on the AMD PBO2 tab. After double-clicking a suggestion, you can go there and see the new value. Save the profile using HYDRA's normal save control to keep your changes for future use.

While building curves, SQ temporarily changes the frequency limit to measure different operating points. It restores the original Fmax after the sweep. You accept CO suggestions separately after the scan finishes.

Before starting: allow enough time

A full test of a 16-core processor can take up to several hours. The initial overall report appears much earlier, but SQ AGENT then builds curves for every core sequentially under two workloads.

Warm-up, transitions between frequency points, and measurement all take time. Duration depends on the number of cores and the number of points before each plateau. Finishing the first stage does not mean the entire test is complete.

Close background benchmarks and demanding tasks during measurement, and keep your usual cooling settings. Avoid changing the profile mid-scan. If you stop the test, you can inspect the overall report and data already measured, but the remaining core curves will be incomplete.

How to read these seven screenshots

Screenshots 1–3 show the overall all-core measurement. Screenshots 4–7 show separate stepped sweeps of C15. In the curve charts, blue means N63 and yellow means SFTv4. Each delta bar compares the core with its CCD median at the same effective frequency, within the same workload.

Screenshot 1. TUNE: the core map and CO suggestions

The first screen answers a practical question: which cores does SQ AGENT suggest adjusting?

Left side: 68 and 61% SQ SCORE 68/100 provides a practical combined assessment of this CPU sample through its behavior and efficiency in this system. Silicon, settings, and cooling affect it. Thermal Match 61% scores temperature uniformity. These are not percentages of CPU performance, and 61% does not mean 61 °C.

Center: two CCDs CCD#0 scores SQ 66.7 and CCD#1 scores 69.3. The large tiles summarize each chiplet. The small tiles show its cores. Core numbering starts at zero.

Bottom right: Core #15 (166) 166 is the core's factory CPPC tag. CO: 0 -> -4 suggests moving from 0 to -4. It is still a suggestion in this screenshot. OK on other tiles means SQ is not suggesting a CO adjustment.

Tile colors and the scale below Blue tiles identify cores that struggle with boost and have lower EF/1V within their CCD: tune C7, C12, C14, and C15 first. Red C0, C10, and C11 show a stronger clock return for their voltage request within their own CCDs. Dark tiles are near the median. The bottom scale shows ΔEF/1V. The lower left records limits from your AMD PBO2 profile, rather than live power or temperature readings.

C15 is one of the cores worth investigating. Suggestions differ: C11 receives 0 -> +4, while C14 receives 0 -> -5. Adjustments can go in either direction because the goal is to bring core behavior closer together.

Blue and red tiles: where tuning starts

Blue tiles are the cores that struggle with boost and need tuning first. They deliver less effective frequency per unit of requested voltage than the typical core in their CCD. These cores can hold boost headroom back. In this example, they are C7, C12, C14, and C15. Start with their CO suggestions and curves.

Red tiles are the cores with the strongest boost return in the displayed group. They deliver more effective frequency per unit of requested voltage than their CCD median. Here, they are C0, C10, and C11. Their behavior helps reveal the group's potential and the direction for bringing other cores closer.

Dark tiles are close to the typical level in their CCD. Usually, start with pronounced blue outliers and then assess the rest of the group. OK means SQ is not suggesting a CO change for that core based on the current result.

Tile color comes from EF/1V: effective frequency divided by VID. Here, “better boost” means a better clock return for the requested voltage within the same CCD. Actual maximum frequency also depends on workload and limits. A blue tile identifies a tuning priority rather than a physically broken core. Blue means the N63 workload on the charts, where color has a different purpose.

Profile limits in the left column

PPT Limit CPU power limit in W. Here, 200 W. A higher limit does not guarantee a gain if another factor already limits boost.

TDC Limit Sustained supply-current limit in A. Here, 160 A.

EDC Limit Peak-current limit in A. Here, 225 A.

THM Limit Profile temperature limit in °C. Here, 80 °C. This is a configured limit, rather than the current temperature.

Fmax Configured upper frequency limit in MHz. Here, 5750 MHz. Actual effective frequency depends on headroom and workload.

FIT The PBO2 scalar affecting the permitted aggressiveness of boost. Here, 1. This is a profile setting, rather than a silicon-quality or CPU-health score.

BCLK Base reference clock used by frequency settings. Here, 100.0 MHz.

ECLK External reference clock when the corresponding mode is active. N/A here means this mode is not in use.

Screenshot 2. DETAILS + Δ Median: what makes a core different

Suggestions give way to each core's deviations from its CCD median during the overall all-core measurement.

The two selectors at the top Report mode = DETAILS, Metric = Δ Median. Core tiles show ΔEF/1V, ΔV, ΔT, and ΔP. This view is for reading data. CO changes belong to TUNE.

The C15 tile at the bottom right ΔEF/1V: -64 MHz, ΔV: +16.0 mV, ΔT: -4.2 °C, ΔP: -0.1 W. This core delivers less frequency per 1 V and requests more voltage than its CCD median, despite running cooler in this measurement.

The CCD#1 tile EFREQ 4924 MHz is the mean effective clock across this CCD's cores. ISO 73.1 scores efficiency with power taken into account. THM 64.7, VID 52.3, and PWR 74.9 score temperature, voltage-request, and power uniformity.

CPPC and TDE CPPC 56.8 scores alignment between factory core ranking and measured behavior. TDE 5/2 is a model-based heat-pattern estimate: possible extra heat generation / possible difficulty removing heat. These indices do not directly measure a cooling fault.

A lower temperature alone does not make C15 more efficient. ΔEF/1V and ΔV already justify examining its curves. A ΔEF/1V of -64 does not mean exactly 64 MHz of lost actual clock speed.

SQ AGENT metrics explainedSQ SCORE and per-CCD SQ

SQ SCORE combines indicators for your particular CPU sample in the current system. It includes efficiency with power taken into account, temperature, VID and power uniformity, frequency consistency, and alignment between factory ranking and measured behavior. The large tiles show a separate score for each CCD.

The scale runs from 0 to 100. Higher is better under comparable conditions. A score of 68 does not mean 68% performance. Silicon, CO, other limits, and cooling all influence the score, making it useful for comparing profiles on the same processor under matching conditions.

EFREQ and EF/1V: actual clocks and voltage return

EFREQ on a CCD tile is the mean of its cores' effective-clock readings during the measurement, in MHz. Effective clock describes the clock actually delivered over the measurement period. It helps assess CPU operation under load.

EF/1V on a core tile is its effective frequency divided by VID. For example, 4900 MHz / 1.10 V gives roughly 4455 MHz per 1 V. A higher value means more clock speed per unit of requested voltage. The tiles abbreviate the unit to MHz, but this is a normalized metric. The Effective frequency axis on the charts shows frequency itself.

ISO: efficiency with power taken into account

ISO asks: how well does this CCD deliver effective frequency relative to its power demand? SQ uses the sum of effective clocks as an indicator of the group's work, relates it to power, and converts the result to a 0–100 score. Higher is better under comparable conditions.

The adjustment is nonlinear. In the current implementation, its basis is the sum of effective clocks divided by power raised to 0.33, with topology scaling and score normalization. ISO 73.1 therefore does not mean 73.1 MHz/W, 73.1 W, or 73.1% energy-conversion efficiency.

In practice, a CO adjustment may produce more effective clock at similar power or maintain clocks while reducing power. ISO helps assess that change. Also check the benefit in the benchmark or task you actually care about.

THM and Thermal Match: temperature uniformity

THM scores temperature uniformity within a CCD. SQ considers both temperature spread and the difference between the hottest and coolest cores. A higher value means more similar thermal behavior among neighbors.

Thermal Match on the left shows the rounded score of the least uniform CCD. Here, CCD#0 has THM 60.7 and CCD#1 has THM 64.7, so the gauge shows 61%. This is a uniformity score, rather than temperature or headroom below a temperature limit. The temperature curves then let you compare cores at the same frequency.

VID and PWR: voltage-request and power uniformity

VID on a CCD tile scores how similar its cores' voltage requests are. Higher means less spread. On an individual core tile, V is the median voltage request in V, while ΔV is its deviation from the CCD median in mV. VID is a request from the core, rather than a separate measurement of the actual supply-rail voltage.

PWR on a CCD tile scores core-power uniformity. A higher score means less relative spread. On a core tile, P is core power in W, and ΔP is its deviation from the CCD median. PWR 74.9 does not mean a power draw of 74.9 W.

CPPC: factory ranking and measured behavior

CPPC is the mechanism through which the processor reports core capabilities and priorities. The number in brackets, such as 166 next to C15, is a factory tag. Higher usually means a preferred core. CPPC #8 in the curve header is the core's position in CPPC order, rather than its physical core number.

CPPC on the large CCD tile is a separate score of how well factory order matches measured clock return for VID, with temperature taken into account. Higher means closer alignment. When it is low, use the actual SQ measurements alongside factory ranking rather than expecting the factory favorite to lead in every profile.

TDE: extra heat generation and heat removal

TDE presents two thermal indices as Leakage / Obstruction. The first estimates the part of elevated temperature that the model associates with the core's power demand. The second estimates residual heat above what the model expects at that power. They are clues about possible extra heat generation and difficulty removing heat.

SQ fits a temperature-versus-power relationship across cores in the same CCD and compares measured temperatures with it. The large CCD tile shows the mean indices across its cores. Here, TDE 5/2 for CCD#1 indicates relatively low values for both components.

Unlike ISO, higher TDE indices mean a stronger thermal deviation that needs attention. A high first index suggests examining VID, CO, and power. A high second index suggests examining thermal behavior and cooling contact. This is model-based diagnosis: it does not directly measure leakage current and cannot, by itself, prove a cooler fault.

CCD MATCH: convergence of the selected curve

CCD MATCH measures the share of comparable core points close to the CCD median at the same effective frequency. SQ calculates a share for N63 and another for SFTv4, then averages those two percentages. It uses valid points from a completed core within overlapping measured ranges.

Tolerances are ±10 mV for VID, ±2 °C for temperature, and ±1 W for power. The metric follows the selected View. Here, C15 has 6% for VID, 6% for temperature, and 75% for power. Zero on a delta chart means the CCD median. N/A means there is insufficient data for that comparison.

A higher MATCH means closer convergence, rather than a percentage of performance. Compare points within the same workload: N63 with N63, SFTv4 with SFTv4. The median is the central, typical value of a measurement set, and Δ means the difference from it.

CO, plateaus, and measurement units

Curve Optimizer shifts a core's V/F curve. A negative value moves it toward lower voltage requests, while a positive value moves it in the other direction. A CO unit is not a fixed number of mV across all frequencies. A suggestion of 0 -> -4 means a new CO value of -4, rather than a 4 mV voltage reduction.

A plateau is reached when a higher frequency limit no longer produces enough effective-clock gain in that workload. The sweep ends, and the chart labels the observed ceiling. A plateau depends on the test conditions and is not a separate stability test.

MHz measures frequency, with 1000 MHz = 1 GHz. V and mV measure voltage, with 1000 mV = 1 V. W measures power, A measures current, and °C measures temperature. N63 and SFTv4 are two different y-cruncher workloads. On the charts, N63 is always blue and SFTv4 yellow.

Screenshot 3. DETAILS + Median: the numbers behind the suggestion

Changing Metric to Median reveals the typical values behind the previous deviations.

C15: four readings EF/1V 4393 MHz, V 1.121 V, T 56.1 °C, P 8.4 W. These are medians from the overall measurement, rather than instantaneous peaks. 4393 is frequency normalized to 1 V.

A comparison with C11 in the same CCD EF/1V 4522 MHz at VID 1.089 V, T 58.8 °C, and P 8.5 W. Cores with similar power readings can still have different voltage requests and different frequency per 1 V.

The large CCD tiles CCD summaries remain the same. Only the presentation of per-core data has changed: absolute medians replace deviations.

C15's elevated VID is visible, but its 56.1 °C reading cannot tell us how it heats up at each frequency. That is what the next stage examines.

Screenshot 4. The C15 curve: where clock gains stop

Further down the page, open Voltage / frequency curves, select CCD#1 and C15, and set View = VID request.

Chart axes The horizontal axis shows requested VID in mV. The vertical axis shows measured effective frequency in MHz. Unlike EF/1V on the core tiles, this is the frequency itself.

Blue and yellow lines Blue N63 reaches 5526 MHz. Yellow SFTv4 reaches 5092 MHz. These are different workloads. Their 434 MHz difference is neither a loss caused by C15 nor a potential gain from a CO change.

The plateau labels SQ raises the frequency limit in steps. When effective clock gains become too small, that workload's sweep ends. The label marks the observed ceiling under these conditions. It does not, by itself, identify which limit caused it.

Header and legend C15, CPPC #8, and CO 0 provide context. CCD MATCH 6% here scores VID convergence. The legend's 49–63 °C for N63 and 47–57 °C for SFTv4 describe temperatures across the displayed points.

The curves reveal C15's operating range and the ceiling for each workload. The next view shows how much extra VID this core requests for the same speed.

Screenshot 5. ΔVID: C15 requests more voltage than its neighbors

Select ΔVID vs CCD median in View. Each bar now tells us how C15's VID differs from the typical value for CCD#1 at that frequency.

The zero line Zero is the CCD median at the same effective frequency in the same test. A bar above zero means an additional voltage request. Frequency now runs along the horizontal axis, replacing VID.

Blue N63 bars The chart scale shows roughly +29…+36 mV. C15 consistently requests more voltage than the CCD#1 median across this range.

Yellow SFTv4 bars The deviations are roughly +8…+25 mV. The trend continues under the second workload. These ranges are approximate readings from the screenshot scale.

CCD MATCH 6% VID tolerance is ±10 mV. Only a small share of comparable points falls within it. This is a curve-convergence statistic, not a percentage of FPS, silicon quality, or lost performance.

The deviation repeats under both workloads. C15 is a convincing candidate for voltage-request adjustment, followed by stability and effective-clock checks.

Screenshot 6. ΔTemperature: VID convergence is only part of the goal

Select ΔTemperature vs CCD median to compare C15's temperature with its neighbors at the same effective frequency.

The vertical scale in °C Zero is the typical CCD#1 temperature at that frequency. Positive values mean C15 runs hotter than the median in the relevant workload.

N63 and SFTv4 N63 shows roughly +3.5…+4.9 °C. SFTv4 starts near +1.0 °C and reaches roughly +4.4 °C. C15 is noticeably hotter at most displayed points.

CCD MATCH 6% Here the label scores temperature convergence with a ±2 °C tolerance. SQ calculates it for the selected metric rather than carrying it over from the VID chart.

Why screenshot 2 showed -4.2 °C Screenshot 2 compared cores under simultaneous all-core load without matching their frequencies. This chart compares separate core sweeps at the same frequency. The different conditions explain the different sign of the temperature deviation.

This captures the central idea of SQ AGENT: when looking for boost headroom, examine convergence in both voltage and temperature curves. A cool core in one operating mode can be a thermal outlier in another.

Screenshot 7. ΔPOW: the power cost of that frequency

The final view, ΔPOW vs CCD median, adds C15's power demand to the picture.

The scale in W Bars above zero mean higher power than the CCD#1 median at the same effective frequency. This is core power, rather than total CPU power.

Two workloads The scale shows roughly +0.7…+1.3 W for N63 and +0.2…+0.9 W for SFTv4. C15 uses additional power in both sweeps.

CCD MATCH 75% Power tolerance is ±1 W. Most comparable points fit inside that tolerance, even though the bars remain positive.

The three charts together VID Match 6%, Temperature Match 6%, and Power Match 75% describe different aspects of core behavior. A higher Power Match does not cancel out an elevated VID or temperature.

C15 combines higher VID, temperature, and power demand at the same speed. That makes it a well-supported candidate for a boost bottleneck. A comparison before and after adjustment is needed to confirm its effect on the whole CCD.

How to use the result in your own tuning

Save the starting profile and run SQ AGENT Save the starting profile from the AMD PBO2 tab. This is the profile SQ AGENT tests. A run includes the overall measurement followed by sequential core curves under N63 and SFTv4. Allow up to several hours for 16 cores. Wait for both workloads to finish for the core you want to compare.

Identify a core that stands out Start with the blue tiles. In DETAILS, inspect ΔEF/1V, VID, and temperature. Then choose the CCD and core on the chart and inspect all four Views. Hover over a point or bar in HYDRA for exact readings. Red cores provide a reference for stronger clock return within the group.

Accept a small CO adjustment After scanning ends, double-click an available suggestion in TUNE to transfer the new CO to that core's settings on the AMD PBO2 tab. Here, C15 receives 0 -> -4. Check the new value in AMD PBO2 and save the profile using HYDRA's normal save control. Clicking again on this result will not add another -4.

Repeat under the same conditions Run SQ again with matching limits and cooling conditions. Compare ISO, CCD uniformity, curve deltas, effective clocks, and the benchmark you care about. Check the new CO for stability under demanding and light loads. The goal is to improve the result that matters while maintaining stability.

The -4 suggestion comes from the overall VID measurement. It is an initial adjustment, rather than an automatic correction for every curve point. If the temperature deviation remains, investigate core behavior and cooling. A repeat SQ run after a cooler change shows how the operating conditions of the same silicon have changed.

The value of SQ AGENT

SQ AGENT helps you understand both the quality of your silicon sample and how the CPU behaves in your cooling system. In this example, we identified C15 and its extra voltage request and temperature at the same speed. Tuning can now start with a specific core and a measured deviation.

The tuning goal: consistent curves inside each CCD and stable performance in your workloads.Technical basis of the example

The example shows HYDRA 2.3C PRO, SQ AGENT 1.3, and a Ryzen 9 9950X3D. All screenshots appear unchanged in order 1–7. SQ metric definitions and user actions follow the HYDRA implementation. Bar ranges are approximate readings from chart scales. This series has no repeat measurement after a CO adjustment, so a specific MHz or performance gain still needs to be measured.

For reference: AMD's official explanations of Precision Boost 2 and Curve Optimizer. The key concepts and workflow are fully explained above.

AMD: how Precision Boost 2 works

AMD Ryzen Master 3.1.0: PBO and Curve Optimizer